Conventional technologies to configure and manufacture high voltage semiconductor power devices are still confronted with difficulties and limitations to further improve the performance due to different tradeoffs. In vertical semiconductor power devices, there is a tradeoff between the drain to source resistance, i.e., on-state resistance, commonly represented by Rao, (i.e., drain-source resistance X Active Area) as a performance characteristic, and the breakdown voltage sustainable by the power device. A commonly recognized relationship between the breakdown voltage (BV) and the RdsA is expressed as: RdsA is directly proportional to BV2.5. For the purpose of reducing the RdsA, an epitaxial layer is formed with a higher dopant concentration. However, a heavily doped epitaxial layer also reduces the breakdown voltage sustainable by the semiconductor power device.
It is within this context that embodiments of the present invention arise.